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Lot M1

  1. Pending Application 13/479,069 filed on 5/23/12   Highly Reliable NAND Flash Memory Using a Five Side Enclosed Floating Gate Storage Elements.  (Continuation of application: 12/082,199 filed on 4/10/2008 [abandoned] which is a continuation of patent 7,376,014)

  2. Patent # 7,376,014      Highly Reliable NAND Flash Memory Using a Five Side Enclosed Floating Gate Storage Elements.     (Filed:  8/18/2006         Issued:  5/2008) 

The above patents 1 and 2 cover a nonvolatile memory that whose reliability and endurance have been improved by reducing the impact of disturbs and also ensuring isolation from neighboring cells. Such a memory made with a floating gate that is spaced away from the diffusions and covered on all five sides except the channel side, by the control gate, there by having increased coupling with the associated advantage of lower high voltages, reduced impact of the unwanted disturb conditions, and providing for improved retention and reliability characteristics at higher operating temperatures is disclosed. The main emphasis in this technology is to provide a device with improved retention, endurance, and temperature characteristics meeting the automotive specifications even with some area penalty

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  1. Patent # 7,583,530    Multi-Bit Memory Technology (MMT) and Cells.  (Filed: 10/2/2006        Issued:  9/2009)
The above patent 3 discusses the method and structures for storing more than one bit in a cell – at differing locations using non-spreading storage medium. Multi-bit storage in a single memory cell is become the norm in the industry. The use of a Nitride layer or a silicon-nodule layer or similar layers capable of location specific charge storage with no spreading, allows easy implementation of multi-bit technology. If the charge is stored in the traps in the Nitride storage layer, a Oxide Nitride Oxide is used as the storage element. If charge is stored in layer of discrete silicon-nodules separated by a thin insulating film, an Oxide silicon-nodule Oxide storage element is used as the storage layer. The exemplary multi-bit cells proposed are programmed by hot electron programming and erased either by using high Voltage tunneling, or by use of a lower voltage MIM Metal-Insulator-Metal Diode carrier generation method and technology called the Tunnel-Gun or TG.
  1. Patent #  7,149,125   Location-Specific NAND (LS NAND) Memory Technology and Cells.       (Filed: 1/19/2006        Issued  12/2006)

  2. Patent # 7,227,786    Location-Specific NAND (LS NAND) Memory Technology and Cells.       (Filed: 7/5/2005        Issued  6/2007)
The above two patents 4 and 5 Provide location specific storage cell structures and operation. These structures use unique low voltage programming and erase methods that are patented. The use of a Nitride layer or a silicon-nodule layer capable of location-specific (LS) charge storage, allow easy vertical scaling and implementation of NOR and NAND NVM array and technology. If the charge is stored in the traps in the Nitride storage layer, a Oxide Nitride Oxide is used as the storage element and if charge is stored in potential wells of discrete silicon-nodules, or Carbon Bucky-ball layers, an Oxide silicon-nodule Oxide storage element, or an Oxide Bucky-ball Oxide layer is used as the storage element.
One of the main problems of the location-specific NAND memory is the inability to erase the cells with repeatable results. A novel erase method, Tunnel Gun (TG) method, that generate holes for consistent erase of LS storage elements and typical NAND Cells that erase by the disclosed method and programmed by either  by Fouler-Nordheim (FN) tunneling or Low Current Hot Electron (LCHE) method are disclosed.

  1. Patent # 7,224,620    CACT-TG (CATT) Low Voltage NVM Cells.   (Filed: 8/18/2006         Issued: 5/2007)

  2. Patent # 7,193,900    CACT-TG (CATT) Low Voltage NVM Cells.    (Filed: 1/18/2005         Issued: 5/2007)
These applications 6 and 7 are applications that cover structure and methods of program and erase based on the CACT and TG Program erase methods for programming and erasing of a non-volatile memory cell. The typical cell described in the example uses the “Channel Accelerated Carrier Tunneling (CACT) method for programming memories”(US patent # 5,519,653 ), which is herby incorporated by reference,  and structural configuration similar to  “Channel Accelerated Tunneling Electron Cell with a Select Region Incorporated for high density low power applications” (US Patent #5,675,161) and “Double Poly Trenched Channel Accelerated Tunneling Electron (DPT-CATE) cell, for memory applications” (US Patent #5,506,431) for accumulating one type of carriers in the floating gate, and another novel method, the Tunnel Gun (Tun-Gun or TG) method  ( US Patents # 6,479,863 B2, US Patent # 6,384,816 B1, and US patent # 6,534,816 B1) for accumulating the other type of carriers in the floating gate of the cells. These methods both require low applied voltages to achieve positive or negative charge accumulation in the floating gate of Non-Volatile Memory cell. The proposed CAcT-Tg or (CATT) cells due to elimination of high voltage requirements are more scalable with the technology and manufacturable easily using currently available process.   These program/ erase methods and cells reduce the requirement of high voltages and currents that are needed for the present day Non-Volatile memory programming. They also provide the ability to have multi-bit storage capability for the cell by providing self-limiting program erase methods. They in addition reduce the complexity of processing of the cells by reducing the high voltage requirements of the junctions in the cell and periphery. Another advantage is the increase in reliability of Cells using this method due to reduced voltage stress.

  1. Patent # 5,506,431    Double Poly Trenched Channel Accelerated Tunneling Electron (DPT-CATE) Cell, For Memory Applications.   (Filed: 5/16/1994          Issued: 4/1996)

  2. Patent # 5,519,653    Channel Accelerated Carrier Tunneling-(CACT) Method For Programming Memories.  (Filed: 3/11/1994          Issued: 5/1996)
Patents 8 and 9 are for low voltage programming applications where the acceleration of the carriers are used to reduce the voltage needed overcome the potential barrier. The patent 8, is the method patent for channel accelerated carrier tunneling method is disclosed and patent application 9 is an application of the method within the NVM to achieve low voltage high speed programming of the cells.

Lot M2

  1. Patent #5,790,455        Low Voltage Single Supply CMOS, Electrically Erasable Read Only Memory.   (Filed: 1/2/1997        Issued: 8/1998)

  2. Patent #5,986,931       Low Voltage Single Supply CMOS, Electrically Erasable Read Only Memory.     (Filed: 7/9/1997        Issued: 11/1999)

  3. Patent #6,201,732       Low Voltage Single Supply CMOS, Electrically Erasable Read Only Memory.      (Filed: 2/2/2000        Issued: 3/2001)

  4. Patent #6,574,140       Low Voltage Single Supply CMOS, Electrically Erasable Read Only Memory.   (Filed: 12/5/2000        Issued: 6/2003)

  5. Patent # 64015 (WO 98/29907) – Singapore     Low Voltage Single Supply CMOS, Electrically Erasable Read Only Memory.   (Issued: 9/2001)

  6. Patent # 110307 -- (Taiwan)    Low Voltage Single Supply CMOS, Electrically Erasable Read Only Memory.    (Issued: 12/1999 & reissue: 2/2002)
The above six patents are for embedded and medium size arrays for non-volatile requirements with very high retention and read-write cycling capability. The typical retention is over 50 years and typically the cells can withstand over million cycles. The technology is applicable for automotive and high temperature applications where current high density technologies cannot be used. By their unique design the cells are not prone to over and under programming problems that plague the standard NVM cells. Hence the cells are programmed and erased using a single DC high voltage application and no pulsed programming with read and re-program is necessary. The cells also are less prone to read and write disturbs.

These cells are not meant for very high density applications as the cell size is larger than those single cells used in high density applications today.

This NVM technology has been licensed to multiple companies in for embedded and medium array applications where reliability and temperature considerations exist.

  1. Patent #6,451,652       Method of Forming an EEPROM Cell Together with Transistor for Peripheral Circuits.    Filed: 9/7/2000        Issued: 6/2003
This method minimizes the masks used by using of self-aligned step during manufacture of the SimpleEE cells, while maintaining the processing sequence of the standard CMOS process.

  1. Patent # 6,411,545    Non-Volatile Latch  (Filed: 11/15/2000     Issued: 6/2002) 
This is a non-volatile latch for high reliability embedded applications.  

Important Note: This set of 8 patents (Memtek LOT 2) has been licensed non exclusively in the past to 7 corporate licensees. The total amount of licensing fees and royalties has been approximately $10M.

Lot M3

  1. Patent # 6,534,816     Method and Apparatus for Injecting Charge onto the Floating Gate of a Nonvolatile Memory Cell. (Filed: 3/1/2000    Issued: 3/2003)

  2. Patent # 6,479,863    Method and Apparatus for Injecting Charge onto the Floating Gate of a Nonvolatile Memory Cell.  (Filed: 12/6/2000    Issued: 11/2002)

  3. Patent # 6,384,451    Method and Apparatus for Injecting Charge onto the Floating Gate of a Nonvolatile Memory Cell.  (Filed: 3/9/2000    Issued:   5/2002)
A tunneling charge injector includes a conducting injector electrode, a grid insulator disposed adjacent the conducting injector electrode, a grid electrode disposed adjacent said grid insulator, a retention insulator which may employ a graded band gap disposed adjacent said grid electrode, and a floating gate disposed adjacent said retention insulator. In the tunneling charge injector, charge is injected from the conducting injector electrode onto the floating gate. Electrons are injected onto the floating gate when the conducting injector electrode is negatively biased with respect to the grid electrode, and holes are injected onto the floating gate when the conducting injector electrode is positively biased with respect to the grid electrode.
The tunneling charge injector is employed in a nonvolatile memory cell having a nonvolatile memory element with a floating gate such as a floating gate MOS transistor. In the nonvolatile memory cell, the floating gate of the tunneling charge injector is coupled to or forms a part of the floating gate of the nonvolatile memory element. The tunneling charge injector is employed to inject charge onto the floating gate of the nonvolatile memory element.

 A memory device includes an array of nonvolatile memory cells wherein each of the memory cells comprises a nonvolatile memory element with a floating gate such as a floating gate MOS transistor and a tunneling charge injector having a floating gate that is either coupled to the floating gate of the nonvolatile memory element or forms a portion of the floating gate of the nonvolatile memory element.

Lot V1

  1. Patent # 6,897,520    Vertically Integrated Flash EEPROM for Greater Density and Lower Cost. Filed: 5/29/2002            Issued:   5/24/2005
A nonvolative memory in the form of a flash EEPROM with high density and low cost. A vertical MOS transistor is formed in well etched into a semiconductor substrate, the substrate having a buried layer of doped material of a first conductivity type acting as the channel region. Source and drain regions of this transistor comprise second conductivity type layers doped in the substrate above and below the buried layer. A thin gate oxide or oxide-nitride-oxide (ONO) layer is formed in the well and a floating gate of polysilicon is formed over the gate oxide. A layer of oxide or ONO is formed over the floating gate, and a second polysilicon or metal layer is used to fill the well to form the control gate and word line. A bit line is formed of a layer of metal or polysilicon deposited over an insulating layer on top of the word line and makes contact with the drain of the vertical MOS transistor through a contact window formed adjacent the well. It achieves a cell size of 2F2 and read speed as DRAM.

 

Please address any inquiries about the above patents to:

Dr. Demetris Paraskevopoulos
Managing Director
Nif/T, LLC
New Business Architects

19160 Bainter Ave., Los Gatos, CA 95030

Phone - 408.395.2160
Fax     - 408.395.2160
Email   - info@nif-t.net


 

 

 

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